asmjit

Provides three distinct emitter abstraction levels (BaseAssembler, BaseBuilder, BaseCompiler) that allow developers to choose between low-level direct instruction encoding to a CodeBuffer, intermediate node-based IR with reordering capabilities, or high-level virtual register allocation with automatic spilling. Each level inherits from the previous, enabling progressive complexity and automation while maintaining control over generated machine code at any abstraction tier.

Implements unified instruction encoding through architecture-specific backends (X86/X64 and AArch64) that use pre-generated opcode lookup tables and instruction signature matching. The X86 backend uses a table generation system that encodes instruction signatures, operand constraints, and opcode patterns into compact lookup structures; AArch64 uses similar table-driven encoding. A single instruction API call (e.g., `mov(dst, src)`) resolves to the correct machine code encoding based on operand types and target architecture.

Implements AArch64 instruction support through a table-driven encoding system similar to x86/x64, with pre-generated instruction signatures and opcode patterns for AArch64 ISA. The AArch64 Instruction Database encodes instruction variants, operand constraints, and encoding rules into lookup tables. At runtime, instruction encoding resolves operand types to the correct AArch64 opcode and encoding format through signature matching.

Abstracts platform-specific virtual memory operations (mmap/mprotect on POSIX, VirtualAlloc/VirtualProtect on Windows) through a unified VirtMem interface. The abstraction handles page allocation, protection transitions, and memory deallocation across operating systems. Platform-specific implementations are selected at compile time based on detected OS, enabling single-source code to work on Linux, Windows, macOS, and other platforms.

Implements a CMake-based build system that enables fine-grained control over compiled features through feature flags (ASMJIT_BUILD_X86, ASMJIT_BUILD_ARM, etc.). Developers can selectively enable/disable architecture backends, instruction databases, and optional features at build time, reducing binary size and compilation time. The build system automatically detects platform capabilities and generates appropriate compiler flags.

The BaseCompiler emitter provides virtual register allocation by allowing developers to request unlimited virtual registers (VReg) that are automatically mapped to physical registers and spilled to stack as needed. The allocator tracks register liveness, performs greedy allocation, and inserts spill/reload instructions transparently. This abstraction hides the complexity of manual register management while maintaining control over register-level optimizations through explicit virtual register declarations.

Manages allocation and lifecycle of executable memory through JitRuntime and JitAllocator, enforcing Write-XOR-Execute (W^X) security semantics where memory is either writable or executable, never both simultaneously. The VirtMem layer abstracts platform-specific virtual memory APIs (mmap on POSIX, VirtualAlloc on Windows) and handles page protection transitions. Code is written to writable memory, then protected as executable before execution, preventing code injection attacks.

BaseBuilder emits instructions as nodes in a linked list (Node system) rather than directly to a buffer, enabling instruction reordering, dead code elimination, and optimization passes before final encoding. Each instruction becomes a Node with metadata about operands, dependencies, and side effects. Nodes can be inserted, removed, or reordered before the builder finalizes code, converting the node graph to machine code through the emitter hierarchy.

Provides a unified operand abstraction (Operand class hierarchy) that represents registers, immediates, labels, and memory references with type safety and architecture awareness. Operands encode register class (GP, XMM, etc.), size, and constraints into a compact representation. Memory operands support complex addressing modes (base + index*scale + displacement) with automatic validation. The operand system enables generic instruction APIs that work across different operand combinations without overloading.

Provides automatic generation of function prologue and epilogue code based on declared calling conventions (x86-64 System V, x86-64 Windows, AArch64 AAPCS). Developers declare function arguments, return values, and clobbered registers; the compiler automatically generates stack frame setup, register saves, and cleanup. This abstraction handles platform-specific calling convention details (argument passing, return value location, stack alignment) transparently.

Implements a label system that enables forward references and code relocation through a two-pass approach: labels are declared during code emission, then resolved during finalization. The CodeHolder maintains a relocation table mapping label references to code offsets. Relocations support multiple types (absolute, relative, section-relative) and are resolved when code is finalized and moved to executable memory, enabling jumps and calls to unresolved targets.

Organizes generated code into sections (code, data, read-only data) within a CodeHolder, enabling separation of concerns and metadata storage. Each section has its own buffer, relocation table, and label namespace. This abstraction allows code generators to emit code and data independently, then combine them during finalization. Sections support different protection levels (executable, writable, read-only) and can be linked together.

Implements a comprehensive x86/x64 instruction database (~1500+ instructions) using a table generation system that derives instruction signatures, operand constraints, and opcode patterns from ISA specifications. The X86 Instruction Database encodes each instruction's valid operand combinations, size variants, and encoding rules into lookup tables. At runtime, instruction encoding resolves operand types to the correct opcode and encoding format through signature matching.