{"passport":{"unfragile":{"@version":"1.0","version":"2026-05","artifact":{"id":"github-asmjit--asmjit","slug":"asmjit--asmjit","name":"asmjit","type":"repo","url":"https://asmjit.com","page_url":"https://unfragile.ai/asmjit--asmjit","categories":["frameworks-sdks"],"tags":["aarch64","asmjit","assembler","code-generation","compiler","cpp","jit","jit-compilation","x86","x86-64","x86-x64"],"pricing":{"model":"open_source","free":true,"starting_price":null},"status":"active","verified":false},"capabilities":[{"id":"github-asmjit--asmjit__cap_0","uri":"capability://code.generation.editing.multi.level.code.generation.abstraction.with.direct.instruction.emission","name":"multi-level code generation abstraction with direct instruction emission","description":"Provides three distinct emitter abstraction levels (BaseAssembler, BaseBuilder, BaseCompiler) that allow developers to choose between low-level direct instruction encoding to a CodeBuffer, intermediate node-based IR with reordering capabilities, or high-level virtual register allocation with automatic spilling. Each level inherits from the previous, enabling progressive complexity and automation while maintaining control over generated machine code at any abstraction tier.","intents":["I need to emit raw x86-64 instructions directly to memory with minimal overhead for performance-critical code","I want to generate code with instruction reordering and optimization passes before finalization","I need automatic register allocation and spilling to avoid manual register management in complex code generation"],"best_for":["JIT compiler developers building scripting engines","performance optimization framework authors","dynamic instrumentation tool builders requiring sub-microsecond code generation latency"],"limitations":["BaseAssembler provides no instruction reordering or optimization — instructions emit in order","BaseBuilder's node-based IR adds memory overhead for intermediate representation storage","BaseCompiler's register allocation uses greedy algorithms, not graph-coloring, limiting optimization for highly register-constrained scenarios","Cross-architecture code generation requires separate emitter instances per target ISA"],"requires":["C++11 or later compiler","Target architecture support (x86/x64 or AArch64)","CodeHolder instance to store generated code and metadata"],"input_types":["operand specifications (registers, immediates, memory references)","instruction mnemonics with operand lists","function signatures with calling convention metadata"],"output_types":["machine code bytes in CodeBuffer","node-based intermediate representation (for Builder)","executable function pointers (after JitRuntime finalization)"],"categories":["code-generation-editing","jit-compilation"],"confidence":0.5,"matches":0,"success_rate":0},{"id":"github-asmjit--asmjit__cap_1","uri":"capability://code.generation.editing.architecture.agnostic.instruction.encoding.with.backend.specific.opcode.tables","name":"architecture-agnostic instruction encoding with backend-specific opcode tables","description":"Implements unified instruction encoding through architecture-specific backends (X86/X64 and AArch64) that use pre-generated opcode lookup tables and instruction signature matching. The X86 backend uses a table generation system that encodes instruction signatures, operand constraints, and opcode patterns into compact lookup structures; AArch64 uses similar table-driven encoding. A single instruction API call (e.g., `mov(dst, src)`) resolves to the correct machine code encoding based on operand types and target architecture.","intents":["I want to write architecture-agnostic code generation logic that works on both x86-64 and ARM64 without conditional branches","I need to validate instruction operand combinations against ISA constraints before encoding","I want to understand which instruction variants are available for a given mnemonic and operand set"],"best_for":["cross-platform JIT compiler developers","portable dynamic code generation frameworks","ISA researchers building multi-target code generators"],"limitations":["Instruction database is static and pre-generated at build time — runtime instruction definition is not supported","X86 instruction encoding handles ~1500+ instructions but excludes some esoteric or vendor-specific extensions","AArch64 backend is less mature than x86/x64 with fewer optimization passes","Operand validation happens at encoding time, not parse time, delaying error detection"],"requires":["C++11 or later","Target architecture backend compiled in (x86/x64 or AArch64)","Knowledge of target ISA operand constraints and calling conventions"],"input_types":["instruction mnemonic (string or enum)","operand list (registers, immediates, memory operands with displacement/scale/index)","operand size hints (8-bit, 16-bit, 32-bit, 64-bit)"],"output_types":["encoded machine code bytes (1-15 bytes for x86, 4 bytes for AArch64)","relocation records for unresolved labels or external references","instruction metadata (size, operand read/write info)"],"categories":["code-generation-editing","data-processing-analysis"],"confidence":0.5,"matches":0,"success_rate":0},{"id":"github-asmjit--asmjit__cap_10","uri":"capability://code.generation.editing.aarch64.instruction.database.with.table.driven.encoding","name":"aarch64 instruction database with table-driven encoding","description":"Implements AArch64 instruction support through a table-driven encoding system similar to x86/x64, with pre-generated instruction signatures and opcode patterns for AArch64 ISA. The AArch64 Instruction Database encodes instruction variants, operand constraints, and encoding rules into lookup tables. At runtime, instruction encoding resolves operand types to the correct AArch64 opcode and encoding format through signature matching.","intents":["I want to emit AArch64 instructions with automatic operand validation and encoding","I need to generate ARM64 code with correct instruction variants based on operand types","I want to support code generation on Apple Silicon, AWS Graviton, or other ARM64 platforms"],"best_for":["ARM64 JIT compiler developers","cross-platform dynamic code generators targeting ARM64","developers building code generators for Apple Silicon or AWS Graviton"],"limitations":["AArch64 backend is less mature than x86/x64 with fewer optimization passes","Some AArch64 extensions (SVE, SME) may have limited support","Instruction database is static and pre-generated at build time","No support for advanced encoding options or instruction fusion"],"requires":["AArch64 backend compiled in","Knowledge of AArch64 instruction set and operand constraints","Target architecture must be AArch64"],"input_types":["instruction mnemonic (mov, add, ldr, etc.)","operand list with types (register, immediate, memory)","operand sizes (32-bit, 64-bit)"],"output_types":["encoded machine code (4 bytes per instruction)","relocation records for immediates or memory operands","instruction metadata"],"categories":["code-generation-editing","data-processing-analysis"],"confidence":0.5,"matches":0,"success_rate":0},{"id":"github-asmjit--asmjit__cap_11","uri":"capability://automation.workflow.cross.platform.virtual.memory.abstraction.with.platform.specific.backends","name":"cross-platform virtual memory abstraction with platform-specific backends","description":"Abstracts platform-specific virtual memory operations (mmap/mprotect on POSIX, VirtualAlloc/VirtualProtect on Windows) through a unified VirtMem interface. The abstraction handles page allocation, protection transitions, and memory deallocation across operating systems. Platform-specific implementations are selected at compile time based on detected OS, enabling single-source code to work on Linux, Windows, macOS, and other platforms.","intents":["I want to allocate executable memory without writing platform-specific code","I need to transition memory from writable to executable with W^X enforcement across platforms","I want to handle platform differences in page size and protection semantics transparently"],"best_for":["cross-platform JIT compiler developers","portable dynamic code generation frameworks","developers targeting multiple operating systems"],"limitations":["VirtMem abstraction is limited to common operations (allocate, protect, deallocate); advanced features (huge pages, NUMA) not supported","Page size is platform-dependent and not configurable","Protection semantics differ slightly across platforms (e.g., Windows requires explicit decommit)","No support for memory mapping files or shared memory"],"requires":["Operating system with virtual memory support (all modern OSes)","Platform detection at compile time (CMake handles this)","C++11 or later"],"input_types":["requested memory size (in bytes)","protection flags (read, write, execute)","alignment requirements"],"output_types":["allocated memory pointer","actual allocated size (rounded to page boundary)","protection state"],"categories":["automation-workflow","safety-moderation"],"confidence":0.5,"matches":0,"success_rate":0},{"id":"github-asmjit--asmjit__cap_12","uri":"capability://automation.workflow.cmake.based.modular.build.system.with.feature.flags","name":"cmake-based modular build system with feature flags","description":"Implements a CMake-based build system that enables fine-grained control over compiled features through feature flags (ASMJIT_BUILD_X86, ASMJIT_BUILD_ARM, etc.). Developers can selectively enable/disable architecture backends, instruction databases, and optional features at build time, reducing binary size and compilation time. The build system automatically detects platform capabilities and generates appropriate compiler flags.","intents":["I want to build asmjit with only the architecture backends I need to reduce binary size","I need to customize the build for embedded systems with limited resources","I want to enable/disable optional features (e.g., instruction validation) at build time"],"best_for":["embedded systems developers with size constraints","developers building minimal JIT runtimes","teams customizing asmjit for specific use cases"],"limitations":["Feature flags are compile-time only — runtime feature detection not supported","Disabling features may break code that depends on them, requiring careful testing","CMake configuration is complex with many options, potentially confusing for new users","No pre-built binary distributions — users must build from source"],"requires":["CMake 3.10 or later","C++11 or later compiler","Platform-specific build tools (make, Visual Studio, etc.)"],"input_types":["CMake feature flags (ASMJIT_BUILD_X86, ASMJIT_BUILD_ARM, etc.)","compiler flags and optimization levels","platform detection results"],"output_types":["compiled asmjit library with selected features","header files with feature-specific declarations","build artifacts (object files, static/shared libraries)"],"categories":["automation-workflow","code-generation-editing"],"confidence":0.5,"matches":0,"success_rate":0},{"id":"github-asmjit--asmjit__cap_2","uri":"capability://code.generation.editing.automatic.register.allocation.with.virtual.register.abstraction","name":"automatic register allocation with virtual register abstraction","description":"The BaseCompiler emitter provides virtual register allocation by allowing developers to request unlimited virtual registers (VReg) that are automatically mapped to physical registers and spilled to stack as needed. The allocator tracks register liveness, performs greedy allocation, and inserts spill/reload instructions transparently. This abstraction hides the complexity of manual register management while maintaining control over register-level optimizations through explicit virtual register declarations.","intents":["I want to generate complex code without manually tracking which physical registers are available","I need automatic spilling to stack when code uses more registers than the architecture provides","I want to declare function arguments and return values with automatic calling convention handling"],"best_for":["JIT compiler developers building expression evaluators or bytecode interpreters","dynamic code generation frameworks targeting multiple architectures","developers prioritizing code generation simplicity over micro-optimized register allocation"],"limitations":["Greedy allocation strategy does not perform graph-coloring or interference analysis, potentially generating suboptimal spill code","Virtual register allocation adds ~5-10% overhead compared to hand-optimized assembly","Spill/reload insertion happens after instruction emission, making it difficult to optimize across spill boundaries","No support for register constraints or hints beyond basic type (integer, float, vector)"],"requires":["BaseCompiler emitter instance","Virtual register declarations via `newReg()` or `newStack()` calls","Target architecture with defined calling conventions (x86-64 or AArch64)"],"input_types":["virtual register requests with type (GP, XMM, YMM, ZMM for x86; GP, FP, NEON for AArch64)","instruction sequences using virtual registers","function prologue/epilogue declarations"],"output_types":["physical register assignments (mapped to actual rax, rbx, etc.)","spill/reload instructions inserted into code stream","stack frame layout with offsets for spilled values"],"categories":["code-generation-editing","planning-reasoning"],"confidence":0.5,"matches":0,"success_rate":0},{"id":"github-asmjit--asmjit__cap_3","uri":"capability://automation.workflow.executable.memory.management.with.w.x.security.enforcement","name":"executable memory management with w^x security enforcement","description":"Manages allocation and lifecycle of executable memory through JitRuntime and JitAllocator, enforcing Write-XOR-Execute (W^X) security semantics where memory is either writable or executable, never both simultaneously. The VirtMem layer abstracts platform-specific virtual memory APIs (mmap on POSIX, VirtualAlloc on Windows) and handles page protection transitions. Code is written to writable memory, then protected as executable before execution, preventing code injection attacks.","intents":["I need to allocate memory for generated code that is protected against code injection attacks","I want to reuse allocated memory for multiple code generation passes without leaking memory","I need to handle platform differences (Linux, Windows, macOS) in executable memory allocation transparently"],"best_for":["security-conscious JIT compiler developers","production runtime environments requiring W^X enforcement","embedded systems with strict memory constraints needing efficient code memory reuse"],"limitations":["W^X enforcement adds page protection overhead (~1-5ms per code finalization) due to mprotect/VirtualProtect syscalls","Memory fragmentation can occur if many small code blocks are allocated, reducing allocator efficiency","JitAllocator uses simple bump-pointer allocation within pages, not best-fit, potentially wasting space","No support for code deallocation or garbage collection — allocated code persists until JitRuntime destruction"],"requires":["Operating system support for virtual memory protection (all modern OSes)","JitRuntime instance to manage allocator lifecycle","CodeHolder with finalized code ready for execution"],"input_types":["CodeHolder with generated machine code","requested memory size (in bytes)","alignment requirements (typically page-aligned)"],"output_types":["executable memory pointer (void*) to generated code","JitAllocator handle for memory lifecycle management","page protection state transitions (writable → executable)"],"categories":["automation-workflow","safety-moderation"],"confidence":0.5,"matches":0,"success_rate":0},{"id":"github-asmjit--asmjit__cap_4","uri":"capability://code.generation.editing.node.based.intermediate.representation.with.instruction.reordering.and.optimization","name":"node-based intermediate representation with instruction reordering and optimization","description":"BaseBuilder emits instructions as nodes in a linked list (Node system) rather than directly to a buffer, enabling instruction reordering, dead code elimination, and optimization passes before final encoding. Each instruction becomes a Node with metadata about operands, dependencies, and side effects. Nodes can be inserted, removed, or reordered before the builder finalizes code, converting the node graph to machine code through the emitter hierarchy.","intents":["I want to optimize generated code by reordering instructions to reduce dependencies and improve ILP","I need to eliminate dead code or redundant instructions after code generation","I want to apply peephole optimizations or instruction fusion before final encoding"],"best_for":["JIT compilers targeting performance-critical code paths","dynamic code generation frameworks with optimization budgets","developers building custom optimization passes for generated code"],"limitations":["Node-based IR adds memory overhead (~40-80 bytes per instruction for node metadata)","Instruction reordering requires dependency analysis, adding compilation latency (~5-15% overhead)","No built-in optimization passes — developers must implement custom passes or use basic reordering","Node graph is mutable only before finalization; post-finalization optimization requires re-emission"],"requires":["BaseBuilder emitter instance (not BaseAssembler)","Understanding of instruction dependencies and side effects","Optional: custom optimization pass implementations"],"input_types":["instruction sequences with operand dependencies","node insertion/removal/reordering operations","optimization pass specifications"],"output_types":["reordered node graph with optimized instruction sequence","machine code after node-to-buffer finalization","optimization metadata (dead code eliminated, instructions fused, etc.)"],"categories":["code-generation-editing","planning-reasoning"],"confidence":0.5,"matches":0,"success_rate":0},{"id":"github-asmjit--asmjit__cap_5","uri":"capability://code.generation.editing.unified.operand.system.with.type.safe.register.and.memory.references","name":"unified operand system with type-safe register and memory references","description":"Provides a unified operand abstraction (Operand class hierarchy) that represents registers, immediates, labels, and memory references with type safety and architecture awareness. Operands encode register class (GP, XMM, etc.), size, and constraints into a compact representation. Memory operands support complex addressing modes (base + index*scale + displacement) with automatic validation. The operand system enables generic instruction APIs that work across different operand combinations without overloading.","intents":["I want to specify instruction operands (registers, immediates, memory) with compile-time type safety","I need to use complex memory addressing modes (e.g., [rax + rbx*4 + 8]) without manual encoding","I want to validate operand compatibility with instructions before encoding"],"best_for":["C++ developers building type-safe code generators","JIT compilers requiring operand validation before instruction emission","developers working with multiple architectures needing unified operand APIs"],"limitations":["Operand validation is architecture-specific and happens at encoding time, not compile time","Memory operand addressing modes are limited to base + index*scale + displacement (no complex expressions)","Operand size inference relies on context (instruction mnemonic), not explicit type annotations","No support for operand constraints beyond basic type (e.g., 'must be even register')"],"requires":["C++11 or later for type-safe operand construction","Knowledge of target architecture register classes and addressing modes","Instruction API that accepts operand types"],"input_types":["register identifiers (rax, rbx, xmm0, etc.)","immediate values (integers, floating-point)","memory operand components (base register, index register, scale, displacement)","label references for jumps and calls"],"output_types":["encoded operand bytes in machine instruction","relocation records for unresolved labels","operand metadata (size, register class, addressing mode)"],"categories":["code-generation-editing","data-processing-analysis"],"confidence":0.5,"matches":0,"success_rate":0},{"id":"github-asmjit--asmjit__cap_6","uri":"capability://code.generation.editing.function.prologue.epilogue.generation.with.calling.convention.support","name":"function prologue/epilogue generation with calling convention support","description":"Provides automatic generation of function prologue and epilogue code based on declared calling conventions (x86-64 System V, x86-64 Windows, AArch64 AAPCS). Developers declare function arguments, return values, and clobbered registers; the compiler automatically generates stack frame setup, register saves, and cleanup. This abstraction handles platform-specific calling convention details (argument passing, return value location, stack alignment) transparently.","intents":["I want to generate functions that follow the target platform's calling convention without manual stack frame management","I need to declare which registers my generated function clobbers so the caller can save them","I want to access function arguments and return values with automatic location mapping"],"best_for":["JIT compilers generating callable functions from bytecode or IR","dynamic code generation frameworks targeting multiple platforms","developers building language runtimes with native code generation"],"limitations":["Calling convention support is limited to standard conventions (System V, Windows x64, AArch64 AAPCS); custom conventions not supported","Stack frame layout is determined by the compiler, not user-configurable","Prologue/epilogue generation assumes standard stack alignment; non-standard alignment requires manual adjustment","No support for variable-length argument lists (varargs) or complex return types (structs by value)"],"requires":["BaseCompiler emitter instance","Target architecture with defined calling convention (x86-64 or AArch64)","FuncSignature declaration with argument and return value types"],"input_types":["function signature (argument types, return type, calling convention)","clobbered register list","stack frame size requirements"],"output_types":["prologue code (stack frame setup, register saves)","epilogue code (register restores, stack cleanup)","argument/return value location mappings (register or stack offset)"],"categories":["code-generation-editing","automation-workflow"],"confidence":0.5,"matches":0,"success_rate":0},{"id":"github-asmjit--asmjit__cap_7","uri":"capability://code.generation.editing.label.based.code.relocation.and.forward.reference.resolution","name":"label-based code relocation and forward reference resolution","description":"Implements a label system that enables forward references and code relocation through a two-pass approach: labels are declared during code emission, then resolved during finalization. The CodeHolder maintains a relocation table mapping label references to code offsets. Relocations support multiple types (absolute, relative, section-relative) and are resolved when code is finalized and moved to executable memory, enabling jumps and calls to unresolved targets.","intents":["I want to emit jumps and calls to labels that haven't been defined yet in the code stream","I need to support code relocation when generated code is moved to different memory addresses","I want to reference external functions or data from generated code with automatic relocation"],"best_for":["JIT compilers with multi-pass code generation","dynamic code generators needing forward references","developers building code generators with complex control flow"],"limitations":["Labels are resolved only at finalization time, not during emission, delaying error detection","Relocation types are limited to common patterns (absolute, relative, section-relative); custom relocations not supported","Forward references require sufficient space for relocation patching (e.g., 5-byte jumps on x86-64), potentially wasting code space","No support for lazy binding or runtime relocation updates"],"requires":["CodeHolder instance to store labels and relocations","Label declarations via `newLabel()` before use","Finalization pass to resolve all relocations"],"input_types":["label identifiers (Label objects)","relocation type specifications (absolute, relative, etc.)","target addresses (code offsets or external references)"],"output_types":["relocation records in CodeHolder","patched machine code with resolved addresses","relocation metadata (type, offset, target)"],"categories":["code-generation-editing","data-processing-analysis"],"confidence":0.5,"matches":0,"success_rate":0},{"id":"github-asmjit--asmjit__cap_8","uri":"capability://code.generation.editing.section.based.code.organization.with.metadata.storage","name":"section-based code organization with metadata storage","description":"Organizes generated code into sections (code, data, read-only data) within a CodeHolder, enabling separation of concerns and metadata storage. Each section has its own buffer, relocation table, and label namespace. This abstraction allows code generators to emit code and data independently, then combine them during finalization. Sections support different protection levels (executable, writable, read-only) and can be linked together.","intents":["I want to separate generated code from constant data and read-only tables","I need to emit code and data in different sections with different protection levels","I want to organize generated code into logical sections (hot path, cold path, data)"],"best_for":["JIT compilers with complex code organization requirements","dynamic code generators separating code from data","developers building code generators with multiple output sections"],"limitations":["Section linking is manual — developers must manage section offsets and cross-section references","No automatic section layout optimization (e.g., cache-aware placement)","Section protection levels are limited to standard types (executable, writable, read-only)","Cross-section references require explicit relocation handling"],"requires":["CodeHolder instance","Section declarations via `newSection()` before emission","Manual section switching during code generation"],"input_types":["section type (code, data, read-only)","section flags (executable, writable, etc.)","code/data to emit to section"],"output_types":["section buffers with code/data","section metadata (offset, size, protection level)","cross-section relocation records"],"categories":["code-generation-editing","automation-workflow"],"confidence":0.5,"matches":0,"success_rate":0},{"id":"github-asmjit--asmjit__cap_9","uri":"capability://code.generation.editing.x86.x64.instruction.database.with.signature.based.encoding","name":"x86/x64 instruction database with signature-based encoding","description":"Implements a comprehensive x86/x64 instruction database (~1500+ instructions) using a table generation system that derives instruction signatures, operand constraints, and opcode patterns from ISA specifications. The X86 Instruction Database encodes each instruction's valid operand combinations, size variants, and encoding rules into lookup tables. At runtime, instruction encoding resolves operand types to the correct opcode and encoding format through signature matching.","intents":["I want to emit x86-64 instructions with automatic operand validation and encoding","I need to understand which operand combinations are valid for a given instruction","I want to generate code that uses the correct instruction variant (e.g., mov vs movzx) based on operand types"],"best_for":["x86-64 JIT compiler developers","dynamic code generators targeting x86-64","developers building x86-64 instruction analysis tools"],"limitations":["Instruction database is static and pre-generated at build time — new instructions require rebuild","Some esoteric or vendor-specific x86 extensions may not be included","Operand validation is signature-based, not constraint-based, limiting expressiveness","No support for instruction prefixes or advanced encoding options (e.g., EVEX for AVX-512)"],"requires":["x86/x64 backend compiled in","Knowledge of x86-64 instruction set and operand constraints","Target architecture must be x86 or x86-64"],"input_types":["instruction mnemonic (mov, add, xor, etc.)","operand list with types (register, immediate, memory)","operand sizes (8-bit, 16-bit, 32-bit, 64-bit)"],"output_types":["encoded machine code (1-15 bytes)","instruction size","relocation records for immediates or memory operands"],"categories":["code-generation-editing","data-processing-analysis"],"confidence":0.5,"matches":0,"success_rate":0}],"trust":{"score":45,"verified":false,"data_access_risk":"high","permissions":["C++11 or later compiler","Target architecture support (x86/x64 or AArch64)","CodeHolder instance to store generated code and metadata","C++11 or later","Target architecture backend compiled in (x86/x64 or AArch64)","Knowledge of target ISA operand constraints and calling conventions","AArch64 backend compiled in","Knowledge of AArch64 instruction set and operand constraints","Target architecture must be AArch64","Operating system with virtual memory support (all modern OSes)"],"failure_modes":["BaseAssembler provides no instruction reordering or optimization — instructions emit in order","BaseBuilder's node-based IR adds memory overhead for intermediate representation storage","BaseCompiler's register allocation uses greedy algorithms, not graph-coloring, limiting optimization for highly register-constrained scenarios","Cross-architecture code generation requires separate emitter instances per target ISA","Instruction database is static and pre-generated at build time — runtime instruction definition is not supported","X86 instruction encoding handles ~1500+ instructions but excludes some esoteric or vendor-specific extensions","AArch64 backend is less mature than x86/x64 with fewer optimization passes","Operand validation happens at encoding time, not parse time, delaying error detection","Some AArch64 extensions (SVE, SME) may have limited support","Instruction database is static and pre-generated at build time","builder identity is not verified yet","no observed match outcomes yet"],"rank_breakdown":{"adoption":0.5862694336303607,"quality":0.35,"ecosystem":0.6000000000000001,"match_graph":0.25,"freshness":0.75,"weights":{"adoption":0.3,"quality":0.2,"ecosystem":0.15,"match_graph":0.3,"freshness":0.05}},"observed_outcomes":{"matches":0,"success_rate":0,"avg_confidence":0,"top_intents":[],"last_matched_at":null},"maintenance":{"status":"active","updated_at":"2026-05-24T12:16:21.549Z","last_scraped_at":"2026-05-03T13:58:37.060Z","last_commit":"2026-03-26T08:20:00Z"},"community":{"stars":4501,"forks":573,"weekly_downloads":null,"model_downloads":null,"model_likes":null}},"distribution":{"claim_url":"https://unfragile.ai/submit?claim=asmjit--asmjit","compare_url":"https://unfragile.ai/compare?artifact=asmjit--asmjit"}},"signature":"cTPErtWVPLMsWW4zGMwpJWzvW5jMC721eYKvZgEipw3pE8j91HOHoSLgHkoX8GjF8ZmwAgUKt6d04GBQ8UjXCw==","signedAt":"2026-06-21T16:52:12.929Z","signedBy":"unfragile.ai","version":1},"_links":{"self":"https://unfragile.ai/api/v1/passport/asmjit--asmjit","artifact":"https://unfragile.ai/asmjit--asmjit","verify":"https://unfragile.ai/api/v1/verify?slug=asmjit--asmjit","publicKey":"https://unfragile.ai/api/v1/trust-passport-public-key","spec":"https://unfragile.ai/trust","schema":"https://unfragile.ai/schema.json","docs":"https://unfragile.ai/docs"}}